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Monday, August 7th, 2017
- AMD Ryzen Threadripper 1950X and 1920X: We’re Allowed To Show Pictures Now
- The AMD Zen and Ryzen 7 Review: A Deep Dive on 1800X, 1700X and 1700
- The AMD Ryzen 5 1600X vs Core i5 Review: Twelve Threads vs Four at $250
- The AMD Ryzen 3 1300X and Ryzen 3 1200 CPU Review: Zen on a Budget
- AMD Launches Ryzen PRO CPUs: Enhanced Security, Longer Warranty
- How To Get Ryzen Working on Windows 7 x64
- AMD Launches Ryzen: 52% More IPC, Eight Cores for Under $330
- The 12-core Core i9-7920X will be available from August 28th
- The 14-18 core parts will be available from September 25th (my birthday…)
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| 9:00a | Toshiba Announces SAS And NVMe Enterprise SSDs With 3D TLC NAND
Toshiba is continuing their series of product announcements featuring their new 64-layer 3D TLC NAND flash memory. With the client SSD for OEMs segments covered by the XG5, BG3 and SG6 and with the TR200 covering the retail SATA market, Toshiba now turns to the enterprise SSD market with a new generation of NVMe and SAS SSDs. The PM5 SAS SSD and CM5 NVMe SSD are based on a new generation of SSD controllers that use the same architecture for both NVMe and SAS, allowing the two product families to share several key features. The PM5 SAS SSD sets new records by offering capacities of up to 30.72 TB in a 2.5" form factor, and sequential transfer speeds of up to 3350 MB/s (reads) thanks to support for four-port SAS MultiLink. SAS has always supported dual-port drives, with the two ports either used in a failover configuration for high availability or bonded for high throughput. When SAS devices were still at 6Gbps there was serious discussion of going beyond two ports per drive and backwards-compatible connectors were standardized, but 12Gbps SAS won out as the preferred next step toward higher throughput. Now that NVMe SSDs using four or more PCIe lanes are providing heavy competition, MultiLink SAS has been dusted off and is being implemented on a SSD for the first time. Existing backplanes will need to be upgraded to physically provide the extra lanes, but otherwise the SAS ecosystem is ready to support 4-port MultiLink drives more or less transparently, since multi-lane/multi-path IO support is already ubiquitous. The CM5 enterprise NVMe SSD will only offer capacities of up to 15.36TB but higher performance than its SAS cousin, including up to twice the random read performance. It supports the latest and greatest NVMe features: scatter-gather lists and Controller Memory Buffer (CMB) for more efficient NVMe over Fabrics use, multiple namespaces and SR-IOV virtualization, and NVMe Management Interface. The CM5 is also previewing a new Persistent Memory Region (PMR) feature that is on track for standardization. The PMR feature appears be an extension of the Controller Memory Buffer feature. CMB allows a NVMe SSD to expose a portion of its DRAM for general-purpose use by other parts of the system. The most common use case so far is with NVMe over Fabrics (NVMeoF) where an RDMA-capable NIC can store data and queued commands straight into the SSD's DRAM with peer-to-peer DMA, eliminating a round-trip to the CPU's DRAM. PMR envisions a different use for the SSD's DRAM by ensuring the buffer's contents are saved to the flash in the event of power loss. This allows the host system to treat the buffer in much the same manner as a NVDIMM providing battery-backed DRAM. The performance of a single drive's PMR won't be competitive with a NVDIMM due to a PCIe x4 link being much slower than a DDR4 bus, but it will provide a small pool of persistent memory that is faster than the drive's block storage accessed through NVMe. Both the PM5 and CM5 implement their host interface's respective standard for streams support, allowing I/O commands to be tagged according to which task they originate from. This allows the SSD to write each task's data to separate parts of the drive, which makes it easier to offer higher and more consistent performance and also can lead to much lower write amplification as data with similar lifetimes is physically grouped together instead of being interleaved within the same erase blocks. The PM5 and CM5 also both support TCG encryption and the relatively new Sanitize command to securely erase not just the flash but all other buffers on the drive, which was not ensured by previous erase methods. The PM5 SAS SSD will be available in capacities from 800GB to 30.72TB, with endurance ratings of 1, 3, 5 and 10 Drive Writes Per Day (DWPD). The CM5 NVMe SSD will be available in capacities from 400GB to 15.36TB with endurance ratings of 1, 3 and 5 DWPD. Both drives use Toshiba's 64-layer TLC BiCS3 3D NAND and are currently sampling to select OEM customers. The timeline for wider availability has not been announced. The SSDs will be on display this week at Flash Memory Summit in Santa Clara, CA. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9:00a | Unannounced AMD Ryzen Threadripper 1920 CPU in Motherboard Support Lists
Three leading makers of motherboards on Friday disclosed specifications of yet-unannounced AMD Ryzen Threadripper 1920 processor. The chip has 12 cores, works at slightly lower frequencies than the model 1920X, but also comes with a lower TDP. Unfortunately, it is unknown when the product is set to become available. So far AMD has publicly introduced three microprocessors in its family of CPUs for super high-end desktops/workstations: the Ryzen Threadripper 1950X (16 cores, 3.4 GHz), the Ryzen Threadripper 1920X (12 cores, 3.5 GHz), and the Ryzen Threadripper 1900X (8 cores, 3.8 GHz base). AMD has never made any announcements regarding any other members in the Ryzen Threadripper family, or if three would be the limit - and it appears there is at least one more incoming. According to CPU support lists of the ASUS ROG Zenith Extreme, ASRock X399 Professional Gaming/X399 Taichi as well as GIGABYTE X399-Gaming 7, which were published this week, the 1920 (without an X) will also make a showing.
The Ryzen Threadripper 1920 will have 12 cores with simultaneous multithreading, a 3.2 GHz base frequency, a 3.8 GHz turbo frequency, and the full 32 MB of L3 cache. The differences between the 1920 and the 1920X are lower clock rates and AMD’s XFR speed boost on the 1920: typically Ryzen CPUs without the X have half the XFR. Another difference is that the AMD Ryzen Threadripper 1920 will have a 140 W TDP, down from 180 W of the higher-end models, due to the lower frequency settings. This is for similar reasons as the 95W/65W TDP differences between the 1700X and 1700. The lower clock speed of the 1920 should be indicative of a slightly lower level of performance than the 1920X, and should mean that it will be cheaper than the 1920X ($799), but somewhat more expensive than the Threadripper 1900X ($549).
The fact that the Ryzen Threadripper 1920 is already supported by motherboards probably means that one can expect its launch in the coming weeks or months, but perhaps not right after the Ryzen Threadripper 1920X and the 1950X that land on August 10. Meanwhile, an interesting point to add here is that the CPU support lists from ASUS, ASRock and GIGABYTE do not indicate they support the 1900X with eight cores, which is announced to be on shelves on August 31st. Related ReadingSources: Motherboard Makers via Hexus. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12:34p | Intel Finalizes Skylake-X Processor Specifications: 18-Cores, 4.4 GHz Turbo, 165W on September 25th
When Intel launched its new high-end desktop platform a few weeks ago, we were provided with Core-X CPUs from quad cores on the latest Kaby Lake microarchitecture, and 6/8/10 core parts on the Skylake-SP microarchitecture derived from the enterprise line and taking a different route to how the cache was structured over Skylake-S. At the time we were told that these latter parts would be joined by bigger SKUs all the way up to 18 cores, and up to $2000. Aside from core-counts and price, Intel was tight lipped on the CPU specifications until today. Skylake-X goes HCCThe original Skylake-X processors up to 10 cores used Intel’s LCC silicon, one of the three silicon designs typically employed in the enterprise space, and the lowest core count. The other two silicon designs, HCC and XCC, have historically been reserved for server CPUs and big money – if you wanted all the cores, you had to pay for them. So the fact that Intel is introducing HCC silicon into the consumer desktop market is a change in strategy, which many analysts say is due to AMD’s decision to bring their 16-core silicon into the market. Both the new HCC-based processors and the recently released LCC-based processors will share the same LGA2066 socket as used on X299 motherboards, and all the processors will differ in core count, with slight variations on core frequencies, TDP and price. The Skylake-X line-up now looks like:
Along with this, we have several release dates to mention. On the specification side, the higher-end CPUs get a kick up in TDP to 165W to account for more cores and the frequency that these CPUs are running at. The top Core i9-7980XE SKU will have a base frequency of 2.6 GHz but a turbo of 4.2 GHz, and a Favored Core of 4.4 GHz. I suspect the turbo will be limited to 2-4 cores of load, however Intel has not listed the ‘all-core turbo’ frequencies which are often above the base frequencies, nor the AVX frequencies here. It will be interesting to see how much power the top SKU will draw. One question over the launch of these SKUs was regarding how much they would impinge into Intel’s Xeon line of processors. We had already earmarked the Xeon Gold 6154/6150 as possible contenders for the high-end CPU, and taking the price out of the comparison, they can be quite evenly matched (the Xeons have a lower turbo, but higher base frequency). The Xeons also come with multi-socket support and more DRAM channels, at +60% the cost. Comparing against AMD’s Threadripper gives the following:
We fully expect the review embargoes to be on the launch dates for each CPU. Time to start ringing around to see if my sample was lost in the post. Related Reading | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1:00p | Microsoft to Enable Eye Control in Windows 10
Microsoft CEO Satya Nadella this past week announced plans to add support for eye tracking to one of the upcoming Windows 10 versions, in a bid to enable disabled people to use computers. The head of Microsoft did not say when the company intended to do this, but only said that the tech would require a compatible eye tracker, such as the Tobii 4C, which is currently supported by some games and may be used to control a Windows-based PC when appropriate software is installed. According to an MSDN blog post, the Eye Control feature has been in development for quite some time — the initial idea to integrate something like that was proposed in 2014. At present, the capability is in beta and interested people can participate in early testing and provide feedback using the Windows Insider program. Microsoft positions the Eye Control primarily as a way to make PCs more accessible to people with disabilities, such as ALS.
Microsoft does not disclose many technical details about its Eye Control feature, but only says that the Tobii Eye Tracker 4C will be one of the compatible eye-tracking devices. Meanwhile, the Tobii 4C is a rather sophisticated piece of hardware that can only be purchased separately (€159 in Europe) for now. By contract, Tobii's previous-gen sensor called EyeX is integrated into various displays and laptops from Acer, Alienware and MSI.
The Tobii 4C is equipped with near-IR 850 nm diodes and an RGB camera to track eye positions, gaze points and head position. With the 4C, Tobii not only switched IR sensors in a bid to get rid of red lights, but also increased polling rate of the device to 90 Hz (up from 60 - 75 Hz on the previous-gen EyeX), which theoretically reduces eye to application latency from 15±5 ms on the previous gen model. The latter factor is important for comfortable interaction with applications and if we are talking about a prolonged usage of a PC by a disabled person, comfort (actually, more like lack of eye fatigue) becomes crucial. Back to hardware. Another important feature of the Tobii 4C is its specially designed EyeChip ASIC (also used in the EyeX) that reduces CPU load and has a built-in “eye-tracking algorithm”. Tobii admits that eye tracking may take up to 10% of a high-end CPU time (1% with the EyeChip), so it is not really a demanding task. However, if hardware processing also reduces input latency, this may be an important factor. After all, Microsoft chose the Tobii platform to develop its Eye Control feature for a reason. The software giant needed a polished-off solution (already compatible with numerous games) that enables certain level of interaction with Windows out-of-the-box. Another advantage of the Tobii could be its hardware-based processing and a relatively low input latency (still 15 ms on the EyeX does not seem very low). Without actual data at hand, it is unclear what Microsoft’s Eye Control feature is going to require. Microsoft wants to make Windows 10 accessible to everyone, so it is highly unlikely that an expensive eye-tracking device will be mandatory. Nonetheless, it is obvious that a typical webcam will not be enough for this feature.
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