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Wednesday, October 23rd, 2019

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12:00a

Arm Announces New Ethos-N57 and N37 NPUs, Mali-G57 Valhall GPU and Mali-D37 DPU

Today Arm is announcing four new products in its NPU, GPU and DPU portfolio. The company is branding its in-house machine learning processor IPs the Ethos line-up detailing more the existing N77 piece and also revealing the smaller N57 and N37 siblings in the family. To top things off, the company is also making ready its first mid-range GPU IP based on the brand-new Valhall architecture, the new Mali-G57. Finally, we’re seeing the release of a new mid-range DPU in the form of the Mali-D37.

Introducing the Ethos NPU Family

Arm’s NPU IP offering was first announced early last year, detailing its architecture a few months later, and has been publicly been known until known just as “Project Trillium”. Arm at TechCon this year has officially branded the IP as the Ethos line-up, and the N77 has been the main product that’s been previously referred to as the Trillium codename.

Microarchitecturally, the new branded Ethos-N77 now publicly changes its specs compared to what had been revealed last year by allowing for a configurable 1 to 4MB SRAM implementation, whilst last year it had been disclosed it would scale up to 1MB only. Arm explains that customers needed more memory bandwidth for processing these mesh networked NPUs, as DRAM bandwidth doesn’t scale up in the premium segment as fast as the core count does. The flagship IP offers up to 4TOPS processing power at 1GHz clock and has a respectable 5TOPS/W efficiency.

Arm is able to use the same building blocks across the different IPs. The NPUs all share the same MAC computation engine (MCE) and programmable layer engines (PLE). The MCE consists out of 128 MAC units, as disclosed last year, and is paired alongside a PLE. An MCE and PLE, plus SRAM, make up a computation engine (CE), and this is the scaling block that differs between the N77, N57 and N37, coming in 16x, 8x and 4x configurations in terms of the CE count.

The mid-range and low-end variants are being released a lot faster than other new IP technologies because Arm is seeing a lot more interest in doing ML in cost-constrained devices where every mm² of silicon is important. Particularly features like smartphone face unlocking or DTV resolution upscaling are becoming commodity features.

The new NPUs have already been licensed and delivered to customers.

Revealing the Mali-G57 - First Mid-range Valhall Based GPU

Earlier this year, Arm had announced the new Valhall architecture in the new Mali-G77 that we’re expecting to see in SoCs next year. The new GPU architecture is a more major departure from the Bifrost based GPUs we’ve seen over the last three years as Arm has completely revamped its graphics ISA and computation microarchitecture.

Today, Arm reveals that the company is adopting the new Valhall architecture in the mid-range, starting off with the new Mali-G57. We currently don’t have too many details on exactly what the finer microarchitecture configurations of the new GPU looks like, but we’re very likely looking at something that will be very similar to the G77, scaled down similar to how the G52 looked like compared to the G72.

Improvements compared to a G52 with three execution engines per core (3EE) promise 1.3x better performance in a similar core configuration, 30% better energy efficiency, and 30% better silicon density (due to the better performance).

Mali-D37 DPU - Bringing High-End Features To the Mid-Range

Finally, to wrap things up, Arm is now bringing to market a new mid-range DPU in the form of the Mali-D37.

The new IP is based on the “Komeda” architecture which was first introduced in the Mali-D71 and its follow-up, the Mali-D77 announced this year. Then new DPU targets resolutions of 2K and FHD and promises to take up only <1mm² on 16nm.

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8:00a

The AUKEY KM-G3 RGB Mechanical Keyboard Review: A Basic Budget Mechanical Keyboard

Today we are taking a look at the KM-G3 RGB Mechanical keyboard from AUKEY, a Chinese manufacturer. Designed as an entry-level mechanical keyboard, AUKEY engineered the KM-G3 to offer mechanical switches and RGB lighting at a significantly lower price than the competition. There aren't any advanced features to speak of, but as a result AUKEY sells the keyboard for just $65, and it is often on sale for even less than that.

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10:00a

TSMC: 5nm on Track for Q2 2020 HVM, Will Ramp Faster Than 7nm

TSMC’s 5 nm (N5) manufacturing technology is projected to provide significant benefits when it comes to performance, power, and area scaling, which is why the contract maker of semiconductors expects a tangible number of its customers to adopt this process. And, with a forecast for aggressive demand paired with some early preparation in installing new equipment, TSMC believes that its N5 technology will ramp even quicker than its 7 nm (N7) process.

In a bid to boost its production capacities, TSMC recently increased its capital expenditures for 2019 from $10 billion - $11 billion to $14 billion - $15 billion. TSMC is particularly invested in buying equipment for its cutting-edge nodes, such as ASML’s Twinscan NXE step-and-scan systems for processes that use extreme ultraviolet lithography (EUVL) for select layers. At present, TSMC’s Fab 15 is making SoCs using N7+, whereas its Fab 18 (the first phase of equipment move-in was completed in March 2019) is on-track to produce N5 chips in high volume starting Q2 2020.

The new tools that will be bought in the coming months are expected to be installed in 2020 and this is when the company will be able to quickly ramp production of chips using its N7, N7+, N7P, N6, N5, and N5P process technologies. The company is confident that it will have a very high market share with its 5 nm nodes.

C.C. Wei, vice chairman and CEO of TSMC, said the following:

First, the 5 nm ramp for next year. Certainly, as compared with six months ago, we are right now more aggressive and more optimistic about it. Hopefully, because we spend big money [...] that it will ramp up much in terms of revenue, be much faster than 7 nm. […] With that money, we spend to buy the tools to prepare everything. We do expect that our growth will go beyond 5% to 10%.

The key difference between N5 and its predecessors that use EUVL is that it is designed to use EUVL on up to 14 layers (up from four and five in case of N7+ and N6). So the ramp of N5 will increase usage of the latest equipment, and to some degree will demonstrate whether EUV tools and ecosystem is ready for prime time or not. Right now, TSMC seems to be very optimistic about EUVL. The light sources it uses offer output power of more than 250 Watts and reach target goals for availability. The company also produces its own pellicles and takes into account characteristics of currently available photoresists.

Mr. Wei said the following:

“We produce our own pellicle. We have a large number of masking capacity and everything. So even photoresist, those kind of things, we have been taking into account. We are in a high-volume production [with] EUV lithography technology. For next year, you have big — even higher volume, and I can assure you that we are all prepared.”

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Sources: Engadget China (via Engadget), VMall (via GSMArena)

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5:45p

Intel Files Antitrust Suit Against SoftBank-Controlled Firm Over Patent Aggregation

Intel this week filed an lawsuit against Fortress Investment Group, a patent assertion entity controlled by SoftBank. Responding to a series of patent infringement lawsuits that Fortress has brought against Intel in recent years, Intel's latest lawsuit accuses Fortress of engaging in anticompetitive behavior, alleging that Fortress stockpiled technology patents in order to patent troll Intel. As a result, Intel is asking the courts to declare Fortress’s patent aggregation business practice as unlawful, and essentially unwind Fortress's operations.

In the recent years IP aggregation with an aim to enforce patents and receive royalties has developed into a business in and of itself. This has lead to the rise of firms known as patent assertion entities (PAEs) — or commonly called patent trolls — who acquire a large number of patents from various companies and then license them (often in package deals) to high-tech companies who are developing actual products.

Through a network of PAEs that Fortress controls, it owns more than a 1,000 U.S. technology patents. Among these are patents originally granted to NXP Semiconductor, giving Fortress a fairly deep collection of chip design patents to enforce. As a result, Fortress (and other PAEs it controls) have previously filed lawsuits against Intel claiming that virtually all CPUs from the company produced since 2011 illegally use the NXP IP.

While Intel is not contesting the validity of the patents themselves, the company is contesting the legality of Fortress's actions with those patents. In its suit, Intel claims that Fortress's patent aggregation business violates Sections 1 and 2 of the Sherman Antitrust Act, as well as Sections 4 and 7 of the Clayton Act (an antitrust law covering unethical business practices), with Intel asking the U.S. District Court for the Northern District of California to act and remedy the situation. Overall, Intel is asking the court to declare Fortress’s patent aggregation business practice as unlawful, declare all patents obtained in violation of the laws as unenforceable, declare all patent contracts and agreements entered into violation of laws as illegal, and transfer all of the claimed patents back to the transferors.

Ultimately, Intel's case rests on the idea that patent enforcement actions by PAEs do not necessarily help to drive innovation by inventors, but rather they hurt manufacturers. As such, what's being called into question is how those patents are being used and enforced, rather than their technical validity. Especially, as Intel insinuates, that Fortress's entire business model is based around the idea of parlaying patents – specifically looking to profit from the spread between what Fortress pays for the patent and what they think they can get companies to settle for out of court (rather than spending even more money defending them in court).

Intel for its part is hardly new at fighting against patent trolls. However, the major complication in this case is that Fortress is a SoftBank business – having been acquired for $3.3 billion back in 2017 – meaning it has the backing of the Japanese conglomerate. So Fortress is far more well heeled than the typical PAE, and SoftBank itself is already a natural competitor to Intel, as it also owns Arm.

Here is what Intel said in its antitrust suit titled ‘Intel Corporation v. Fortress Investment Group LLC et al’ (5:2019cv06856):

Intel brings this complaint to end a campaign of anticompetitive patent aggregation by Fortress and a web of PAEs that Fortress owns or controls. […]

Through its anticompetitive aggregation scheme, Fortress has engaged in anticompetitive conduct in creating a portfolio of patents that purportedly read on electronic devices and components or software therein and processes used to manufacture them that allows it to charge far more than the value of the inventive contributions (if any) of the patents and of competitive prices for licenses. Fortress and its PAEs seek to use that ill-gotten power to extract and extort exorbitant revenues unfairly and anticompetitively from Intel, and other suppliers of electronic devices or components or software for such devices and ultimately from consumers of those products. Fortress’s aggregation is thus intended for an anticompetitive purpose — to invest in patents at costs lower than the holdup value of the patents to ensnare as many potential licensees as possible and to allow it and its PAEs to assert as many possible claims of infringement to tax the commercial use of existing technology at rates beyond the actual value (if any) of the aggregated patents. […]

Intel brings this action to remedy the harms that it has already suffered from Defendants’ violations of federal antitrust and state unfair competition laws and to prevent further harm to itself, the broader electronics industry, and U.S. consumers.

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Source: Reuters, USCourts.Gov

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6:00p

Samsung Announces Exynos 990: 7nm EUV, M5, G77, LPDDR5 Flagship SoC alongside Exynos 5123 5G Modem

Today Samsung unexpectedly announced the brand new Exynos 990 chipset – likely to be Samsung’s flagship SoC for 2020, employing the newest IP and offering the newest features on the 7nm EUV manufacturing node. The chip closely follows the release of the Exynos 980 earlier in September, and both new silicon chips bring with them 5G connectivity alongside their new product naming scheme.

Samsung Exynos SoCs Specifications
SoC	Exynos 990	Exynos 9820 / 9825
CPU	2x Exynos M5 @ ? GHz (+20% perf) 2x Cortex A76 @ ? GHz 4x Cortex A55 @ ? GHz	2x Exynos M4 @ 2.73 GHz 2x 512KB pL2 3 MB L3 2x Cortex A75 @ 2.31 / 2.4GHz 2x 256KB pL2 4x Cortex A55 @ 1.95 GHz No pL2's 1MB L3
GPU	Mali G77MP11 @ ? MHz	Mali G76MP12 @ 702 MHz
Memory Controller	LPDDR5 @ 2750MHz	4x 16-bit CH LPDDR4X @ 2093MHz 2MB System Cache
ISP	Single: 108MP Dual: 24.8MP+24.8MP	Rear: 22MP Front: 22MP Dual: 16MP+16MP
NPU	Dual NPU + DSP >10 TOPs	Dual NPU 1.86 TOPs
Media	8K30 & 4K120 encode & decode H.265/HEVC, H.264, VP9	8K30 & 4K150 encode & decode H.265/HEVC, H.264, VP9
Modem	Exynos Modem *External* (LTE Category 24/22) DL = 3000 Mbps 8x20MHz CA, 1024-QAM UL = 422 Mbps ?x20MHz CA, 256-QAM (5G NR Sub-6) DL = 5100 Mbps (5G NR mmWave) DL = 7350 Mbps	Exynos Modem Integrated (LTE Category 20/20) DL = 2000 Mbps 8x20MHz CA, 256-QAM UL = 316 Mbps 3x20MHz CA, 256-QAM
Mfc. Process	Samsung 7nm LPP (EUV)	Samsung 8nm LPP / 7nm LPP (EUV)

Starting off with the new CPU complex, Samsung seemingly is continuing with their custom CPU designs for this generation, and we’re seeing the deployment of the new Exynos M5 microarchitecture. Samsung quotes that the new design is 20% faster than the Exynos M4 in the 9820 – a bit of a conservative figure given the larger process node improvement. The new CPU will have to compete against the next generation Snapdragon flagship which most likely will come with Cortex-A77 derived cores which promises 23-30% IPC increases – unless that chip comes with clock degradations, the new M5 will have a hard time competing.

Samsung has upgraded the middle core from the Cortex A75 in the previous generation a newer Cortex A76 design, which should provide a more significant performance uplift in every-day workloads. Finally, we continue to see Cortex A55 cores as the little efficiency cores. Samsung doesn’t disclose the clock frequencies of any of the CPU clusters, but advertises that the overall improvement of the new tri-cluster is 13%.

The Exynos 990 sees a big GPU upgrade in the form of the new Mali-G77 in an MP11 configuration. The new Valhall architecture promises to be a very large performance jump for Arm’s GPU IP, and it looks like the new Exynos will be amongst the first chipsets to employ the new GPU family. Samsung press release claims we’ll see performance uplifts of up to 20%, or power efficiency gains of up to 20%. The increase seems quite meagre given the process improvement as well as the new GPU architecture, it seems very unlikely Samsung will be able to catch up to Apple’s newest chipsets – and Qualcomm is expected to have a big generational jump as well.

One fundamental change that the Exynos 990 brings with itself is the transition from LPDDR4X memory to LPDDR5 memory. This allows the new chipset to increase the memory controller frequency from 2093 MHz to 2750MHz and we’re also expecting the new DRAM technology to bring power efficiency gains to the table.

Samsung discloses that the chip comes with a dual-core NPU and a new DSP which can perform over 10 TOPs in computational throughput – it’s not exactly clear here if Samsung is referring to the DSP’s capability or the combined capabilities of the NPU and DSP. The Exynos 9820’s NPU had a throughput of 1.86TOPs.

Finally, what’s odd here is the chip’s connectivity capabilities: Samsung doesn’t list the Exynos 990 as having modem capabilities which might point out that we’re maybe looking at a pure application processor this generation. Instead of an integrated modem, Samsung is advertising the new Exynos Modem 5123 as a new discrete chipset:

The new modem iterates on the Exynos Modem 5100 used this year: It’s still a complete multi-band solution supporting everything from 2G to 5G sub-6 as well as mmWave, however Samsung has massively upgraded the new chip’s maximum throughput. In regular 4G LTE, the new chip now supports downlink speeds of up to 3Gbps while offering 422Mbps upload. In 5G sub-6, we’re seeing 5.1Gbps downloads, and 7.35Gbps in mmWave networks. The chip’s speeds are enabled by up to 8x carrier aggregation and a new higher-order 1024 QAM, which is as far as we know, the first modem to be announced with such capabilities.

Samsung’s choice of going with a discrete 5G modem this generation seems to be related to the economics of the new silicon: The new 5G modems are still quite large in die size, although the Exynos Modem 5100 was amongst the smallest at 56.03mm². Still, both the new modem as well as the Exynos 990 are manufactured on Samsung’s 7nm EUV node, and separating the two into discrete chips likely makes sense at this point in time in order to offer more flexibility and to increase manufacturing yield.

One question which remains open, is whether Samsung will be opting to pair the Exynos 990 with a different modem than the 5123. Still, it’s unlikely that we’ll see any pairing with a 4G modem, meaning all Exynos flagship devices next year will have 5G support.

Samsung says we’ll see the Exynos 990 in mass production by the end of the year, and we’re likely have the Galaxy S11 being powered by the new piece.

Introducing the Ethos NPU Family

Revealing the Mali-G57 - First Mid-range Valhall Based GPU

Mali-D37 DPU - Bringing High-End Features To the Mid-Range

Related Reading

Related Reading

Exynos 990

Exynos 9820 / 9825

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