[$] Detecting and handling split locks
The Intel architecture allows misaligned memory access in situations
where other architectures (such as ARM or RISC-V) do not. One such
situation is atomic operations on memory that is split across two cache
lines. This feature is largely unknown, but its impact is even less so. It
turns out that the performance and security impact can be significant,
breaking realtime applications or allowing a rogue application to slow the
system as a whole. Recently, Fenghua Yu has been working on detecting and
fixing these issues in the split-lock
patch set, which is currently on its eighth revision.