Decadent Singularity

To cite ChatGPT
ARM was designed to eliminate unnecessary the branches killing pipeline, so most opcodes (even syscalls) could be executed conditionally. That surprisingly makes assembly code unusually readable compared to other say MIPS or x86. ARM also allows loading and storing multiple registers per opcode. That is kinda useful for stuff like memcpy and SIMD code. That is how 80ies RISC OS games managed to pull out real time 3d graphics with textured surfaces (ARM's fill rate was 4x the x86, bottlenecking on memory latency).

In ARM assembly language, condition codes are used to specify the condition under which an instruction should be executed. These condition codes are appended to the end of mnemonics in ARM assembly instructions. There are four basic condition codes and one special condition code in ARM:

EQ - Equal: This condition code is used when you want to test if two values are equal. It is represented by the mnemonic suffix "EQ." For example, "BEQ" means "Branch if Equal."

NE - Not Equal: This condition code is used when you want to test if two values are not equal. It is represented by the mnemonic suffix "NE." For example, "BNE" means "Branch if Not Equal."

GT - Greater Than: This condition code is used when you want to test if one value is greater than another. It is represented by the mnemonic suffix "GT." For example, "BGT" means "Branch if Greater Than."

LT - Less Than: This condition code is used when you want to test if one value is less than another. It is represented by the mnemonic suffix "LT." For example, "BLT" means "Branch if Less Than."

AL - Always: This is a special condition code that indicates that the instruction should always be executed regardless of the condition. It is often used without explicitly specifying it in mnemonics because it's the default condition. For example, "ADD" without a condition code suffix means "Add always."

These condition codes are used in conditional branching instructions, such as "BEQ," "BNE," "BGT," and "BLT," as well as in other instructions that can be conditionally executed based on the status flags in the processor's CPSR (Current Program Status Register).

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